Description
Kforce's client, a growing and established engineering technology company is seeking Senior or Principal Signal & Power Integrity Engineer in Chandler, AZ area.Summary:We are working directly with the Hiring Manager on this search assignment.

We have been working with this client for several years and have made numerous placements. We are seeking someone with a strong experience in signal and power integrity related to semiconductor IC package design or similar. This position is hybrid remote.

Responsibilities:* As a Senior or Principal SI/PI Engineer, you will work with IC package design engineers to provide design solutions for high-speed and low speed signals, clocks, power delivery signals, and power and ground planes* Provide routing guidelines for high-speed, low-speed, power signals, power, and ground planes from bumps to balls* Work directly with our customers, package design engineers, simulation engineers, business units, R&D, and assembly* Provide package layer counts, stack ups, materials, impedance control, test impedance targets, and optimizing net assignments for signals* Senior or Principal SI/PI Engineers will perform SIPI simulation/optimization to make sure critical signals meet their required specifications* Signal integrity analysis of frequency and time domain simulations for high-speed signals and low speed signals following specifications* Optimize single ended or differential Insertion loss, return loss, X-talk, and power sum X-talk for differential signaling groups and protocols* IR_DROP simulation for the power rails from bumps to balls* AC frequency sweep simulation to optimize the high RLC traces to the lower by achieving low resistance and inductance traces* Power plane resonance to measure the resonances of the package plans* PDN frequency domain and transient time domain analysesRequirements* Bachelor's or Master's degree in Electrical Engineering, Physics, Computer Engineering or similar field* At least 5 to 10+ years of Signal and Power Integrity Engineering experience or similar* Experience with package layout tools such as Cadence APD, SiP or similar tools* Experience with high-speed bus design compliance such as DDR5, PCIe5, 56 GBPS and 112 GBPS PAM4* Experience working with customers, global design & simulation teams and/or EDA tool vendors* Experience/knowledge of next generation advanced high speed package design/simulation to meet electrical performance or similar* Strong background in the application of Electromagnetics and High-Speed Transmission Line principles related to signal and power integrity* Proficiency in time and frequency domain modeling and use of 2D and 3D simulation tools such as Ansys HFSS, SIwave, Cadence/Sigrity, ADS* Demonstrated and effective verbal/written communication skills* Excellent analytical and problem-solving skills* Ability to perform as an individual contributor and team player* Understanding of the SI and PI associated with bump signals/ground patterns and ability to optimize the balls signal/ground placement to improve the performance is a plus but not requiredJob TypeDirect HireCompensation150000 - $185000.